1. Field of the Invention
This invention relates generally to bipolar random access memory (RAM) circuits and, more particularly, to a selectable current source for writing individual cells of the RAM.
2. Background Art
Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
There are many types of memory cells known in the art. Typically, two multi-emitter NPN transistors have their bases coupled to the collector of the other transistor. One emitter of each transistor is coupled to a lower word line and a second emitter of each transistor is coupled to a first and a second bit line, respectively. The bit lines may alternatively be referred to as column select lines. Two PNP load transistors have their emitters connected to an upper word line. The base and collector of each PNP transistor is connected to the collector and base, respectively, of each of the NPN transistors.
A row of cells is selected when increased voltage is supplied to the upper word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly to the sense amplifier. A second read current through the other bit line flows through one side of the memory cell to the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed to the sense amplifier.
However, the PNP transistors in each memory cell have a relatively large diffusion capacitance that must be charged by the first read current. This turns on the lateral PNP transistor's collector current which discharges the previously on PNP transistor's diffusion capacitance. To minimize this charge storage, the bit line currents could be reduced, but this would cause slower read access times. The read current must be approximately 0.5 microamps to give a fast access time. Therefore, conventional circuitry increases the current by the addition of a write current only during the write mode for charging and discharging this charge storage and aiding in writing the cell quickly. This write current would flow to the bit line only during the write mode (about 10 to 25 nanoseconds in duration). Previously known circuitry include a first and a second current source for providing an additional write current to one or both of the bit lines. The first and second current sources are "on" continuously, merely steering the write current from a load to the appropriate bit lines. The first and second write currents are steered by a column decode circuit. The column decode circuit includes a transistor having a collector coupled to the bit line leading to the memory cell and sense amplifier, and an emitter coupled to the first or second current source. The base-emitter capacitance of each of these transistors must be discharged before the write current will flow. This capacitance is equal to the summation of the base-emitter capacitance of each transistor in each bit line. The value of this capacitance increases as the size of the array increases.
Therefore, a memory cell array is needed having a circuit that provides a selectable write current that is substantially greater in amplitude than the read current and only flows during the write mode.